1. Field of the Invention
The present invention relates to a sensing circuit for sensing currents, particularly of the type used in semiconductor memory devices, such as non-volatile memory devices, for accessing memory cells in reading.
2. Description of the Related Art
A sensing circuit for semiconductor memory devices includes a plurality of sense amplifiers and, during a reading operation, every sense amplifier compares the current flowing through a respective selected memory cell (memory cell current) with a comparison current, for discriminating the content of the selected memory cell. A current/voltage (I/V) converter, usually implemented by transistors connected in current-mirror configuration, converts the memory cell and comparison currents into corresponding voltage signals, which are fed to a voltage comparator. In particular, the memory cell current is provided to an input circuit branch of the I/V converter, in such a way as to be mirrored on an I/V converter output circuit branch receiving the comparison current. The voltage comparator is connected to respective nodes of the input and output branches of the I/V converter and provides an output binary signal, function of the difference between the memory cell current and the comparison current, thus corresponding to the content of the memory cell.
Typically, the comparison current is obtained from a reference current, provided by a reference cell structurally identical to the memory cells to be read. In detail, a voltage generator receives the reference current and converts it into a suitable drive voltage for a transistor which provides the comparison current to the I/V converter output circuit branch.
In a solution known in the art, the voltage generator comprises a circuit similar to the I/V converter, i.e. having a current-mirror architecture. Particularly, the voltage generator includes a main circuit branch coupled to the reference cell and a mirroring circuit branch in parallel to the main branch, on which the reference current is mirrored. A suitable node of the mirroring branch provides the drive voltage corresponding to the reference current.
In order to limit the energy consumption, the voltage generator is usually kept switched off, to be switched on when the memory device is accessed for a reading operation. The switching-on time of the voltage generator is critical for the access time of the memory device, because, in order to have a correct reading, the comparison current, and thus the drive voltage of the transistor generating it, has to rapidly reach the prescribed, steady state value.
A setting time of the voltage generator is influenced by its output capacitive load, which depends on several factors, particularly on the size and the data parallelism of the memory device. In fact, the voltage generator is usually common to all the sense amplifiers of the memory device and, in the case of large memory devices having high data parallelism, it has to drive a great capacitive load; this increases the setting time of the generated voltage. A long setting time impacts on the access time of the memory device and favors an error probability of a reading operation.
On the other hand, if, in order to reduce the setting time, the output parasitic capacitances of the voltage generator are kept low, the resulting generated voltage would be affected by noise. In fact, a further drawback of the use of current mirror circuits for the voltage generator is the typical poor noise rejection versus the reference voltage (ground) or the supply voltage. Especially in presence of low capacitive loads, a poor noise rejection impairs the operation of the sensing circuit by further increasing the reading error probability.
For a best buffering of the drive voltage, an alternative solution is to exploit a plurality of mirroring circuit branches in parallel to the main circuit branch in the voltage generator. However, this contrasts to the requirement of minimizing the semiconductor area occupied by the memory device.
Accordingly, there exists a need for overcoming the disadvantages of the prior art as discussed above.